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E40 Process Jobs + E94 Control Jobs + E30 communication state

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GEM300 layer: SEMI E40-0705 Process Job and E94-0705 Control Job
state machines, plus the E30 §6.1 communication-state machine that
sits between HSMS SELECT and full GEM communication. Data-driven
via data/process_job_state.yaml and data/control_job_state.yaml,
mirroring the existing control_state.yaml pattern.

Wire coverage:
  S14F9/F10   CreateObject (CJ)              host -> equipment
  S14F11/F12  DeleteObject (CJ)              host -> equipment
  S16F5/F6    PRJobCommand                   host -> equipment
  S16F9       PRJobAlert                     equipment -> host
  S16F11/F12  PRJobCreate (simplified body)  host -> equipment
  S16F13/F14  PRJobDequeue                   host -> equipment
  S16F27/F28  CJobCommand                    host -> equipment

Process Job FSM exposes 8 states matching PRJOBSTATE bytes (E40 §10.3.2);
HOQ is reorder-aware (move-to-head against an insertion-order vector);
Stop/Abort on a Queued PJ routes through ABORTING so the host observes
PRJOBSTATE=7 on the wire (§6.3); alert_enabled is settable per-PJ for
PRALERT control; FSM dispatches through ProcessJobStore::on_change_
dynamically so a late set_state_change_handler() reaches existing PJs.

Hardening: loader rejects NoState (sentinel) as initial/from/to and
rejects `on: created` rows; static_asserts pin enum values to wire
bytes; ProcessJobStore is non-movable to keep the per-PJ this-capture
safe.

Server simulator cascades the full CJ -> PJ lifecycle on CJSTART so
the wire trace exercises every legal state. CEIDs 400/401 fire on CJ
state changes via the existing event-report pipeline.

Tests: 60+ new assertions across test_process_jobs, test_control_jobs,
test_communication_state, test_hsms_connection, plus loader and
messages round-trip coverage.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
This commit is contained in:
Raphael Maenle
2026-06-07 21:00:32 +02:00
parent 1f67aad985
commit 90c177b7ce
33 changed files with 3122 additions and 62 deletions
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tests/test_secs2.cpp
+36
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@@ -97,3 +97,39 @@ TEST_CASE("SML rendering") {
Item body = Item::list({Item::ascii("MDLN"), Item::u4(uint32_t{42})});
CHECK(to_sml(body) == "<L [2] <A \"MDLN\" > <U4 42 > >");
}
TEST_CASE("JIS-8 encode/decode (E5 §9.5)") {
// Format byte for JIS-8 = 0x11 << 2 | 0x01 = 0x45 with 1-byte length.
// 3 bytes payload "abc" (we don't bother with real JIS chars; the wire
// format is byte-identical to ASCII, only the format code differs).
Item j = Item::jis8("abc");
auto bytes = encode(j);
CHECK(bytes == std::vector<uint8_t>{0x45, 0x03, 'a', 'b', 'c'});
Item back = decode(bytes);
CHECK(back.format() == Format::JIS8);
CHECK(back == j);
}
TEST_CASE("C2 (Unicode 2-byte) encode/decode (E5 §9.5)") {
// 0x12 << 2 | 0x01 = 0x49 format byte, 1-byte length, then 2 bytes per
// code point big-endian. Code points: U+00E9 (é), U+4E2D (中).
Item c = Item::c2({0x00E9, 0x4E2D});
auto bytes = encode(c);
CHECK(bytes == std::vector<uint8_t>{0x49, 0x04, 0x00, 0xE9, 0x4E, 0x2D});
Item back = decode(bytes);
CHECK(back.format() == Format::C2);
CHECK(back == c);
}
TEST_CASE("JIS-8 and C2 disambiguate from ASCII / U2 by Format") {
// Same backing storage, different format code → not equal.
CHECK(Item::jis8("hi") != Item::ascii("hi"));
CHECK(Item::c2({0x41, 0x42}) != Item::u2({0x41, 0x42}));
}
TEST_CASE("SML rendering tags JIS-8 with J and C2 with C") {
CHECK(to_sml(Item::jis8("hi")) == "<J \"hi\" >");
CHECK(to_sml(Item::c2({0x41, 0x42})) == "<C 65 66 >");
}